251 lines
9.3 KiB
C++
251 lines
9.3 KiB
C++
/* ========================================================================
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(C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the authors be held liable for any damages
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arising from the use of this software.
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Please see https://computerenhance.com for more information
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======================================================================== */
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/*
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NOTE(casey): This instruction table is a direct translation of table 4-12 in the Intel 8086 manual.
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The macros are designed to allow direct transcription, without changing the order or manner
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of specification in the table in any way. Additional "implicit" versions of the macros are provided
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so that hard-coded fields can be supplied uniformly.
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The table is also designed to allow you to include it multiple times to "pull out" other things
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from the table, such as opcode mnemonics as strings or enums, etc.
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*/
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#ifndef INST
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#define INST(Mnemonic, Encoding, ...) {Op_##Mnemonic, Encoding, __VA_ARGS__},
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#endif
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#ifndef INSTALT
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#define INSTALT INST
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#endif
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#define B(Bits) {Bits_Literal, sizeof(#Bits)-1, 0, 0b##Bits}
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#define D {Bits_D, 1}
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#define S {Bits_S, 1}
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#define W {Bits_W, 1}
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#define V {Bits_V, 1}
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#define Z {Bits_Z, 1}
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#define XXX {Bits_Data, 3, 0}
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#define YYY {Bits_Data, 3, 3}
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#define RM {Bits_RM, 3}
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#define MOD {Bits_MOD, 2}
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#define REG {Bits_REG, 3}
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#define SR {Bits_SR, 2}
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#define ImpW(Value) {Bits_W, 0, 0, Value}
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#define ImpREG(Value) {Bits_REG, 0, 0, Value}
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#define ImpMOD(Value) {Bits_MOD, 0, 0, Value}
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#define ImpRM(Value) {Bits_RM, 0, 0, Value}
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#define ImpD(Value) {Bits_D, 0, 0, Value}
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#define ImpS(Value) {Bits_S, 0, 0, Value}
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#define DISP {Bits_Disp, 0, 0, 0}
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#define ADDR {Bits_Disp, 0, 0, 0}, {Bits_DispAlwaysW, 0, 0, 1}
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#define DATA {Bits_Data, 0, 0, 0}
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#define DATA_IF_W {Bits_WMakesDataW, 0, 0, 1}
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#define Flags(F) {F, 0, 0, 1}
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INST(mov, {B(100010), D, W, MOD, REG, RM})
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INSTALT(mov, {B(1100011), W, MOD, B(000), RM, DATA, DATA_IF_W, ImpD(0)})
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INSTALT(mov, {B(1011), W, REG, DATA, DATA_IF_W, ImpD(1)})
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INSTALT(mov, {B(1010000), W, ADDR, ImpREG(0), ImpMOD(0), ImpRM(0b110), ImpD(1)})
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INSTALT(mov, {B(1010001), W, ADDR, ImpREG(0), ImpMOD(0), ImpRM(0b110), ImpD(0)})
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INSTALT(mov, {B(100011), D, B(0), MOD, B(0), SR, RM, ImpW(1)}) // NOTE(casey): This collapses 2 entries in the 8086 table by adding an explicit D bit
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INST(push, {B(11111111), MOD, B(110), RM, ImpW(1)})
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INSTALT(push, {B(01010), REG, ImpW(1)})
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INSTALT(push, {B(000), SR, B(110), ImpW(1)})
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INST(pop, {B(10001111), MOD, B(000), RM, ImpW(1)})
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INSTALT(pop, {B(01011), REG, ImpW(1)})
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INSTALT(pop, {B(000), SR, B(111), ImpW(1)})
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INST(xchg, {B(1000011), W, MOD, REG, RM, ImpD(1)})
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INSTALT(xchg, {B(10010), REG, ImpMOD(0b11), ImpW(1), ImpRM(0)})
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INST(in, {B(1110010), W, DATA, ImpREG(0), ImpD(1)})
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INSTALT(in, {B(1110110), W, ImpREG(0), ImpD(1), ImpMOD(0b11), ImpRM(2), Flags(Bits_RMRegAlwaysW)})
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INST(out, {B(1110011), W, DATA, ImpREG(0), ImpD(0)})
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INSTALT(out, {B(1110111), W, ImpREG(0), ImpD(0), ImpMOD(0b11), ImpRM(2), Flags(Bits_RMRegAlwaysW)})
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INST(xlat, {B(11010111)})
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INST(lea, {B(10001101), MOD, REG, RM, ImpD(1), ImpW(1)})
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INST(lds, {B(11000101), MOD, REG, RM, ImpD(1), ImpW(1)})
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INST(les, {B(11000100), MOD, REG, RM, ImpD(1), ImpW(1)})
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INST(lahf, {B(10011111)})
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INST(sahf, {B(10011110)})
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INST(pushf, {B(10011100)})
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INST(popf, {B(10011101)})
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INST(add, {B(000000), D, W, MOD, REG, RM})
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INSTALT(add, {B(100000), S, W, MOD, B(000), RM, DATA, DATA_IF_W})
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INSTALT(add, {B(0000010), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(adc, {B(000100), D, W, MOD, REG, RM})
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INSTALT(adc, {B(100000), S, W, MOD, B(010), RM, DATA, DATA_IF_W})
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INSTALT(adc, {B(0001010), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(inc, {B(1111111), W, MOD, B(000), RM})
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INSTALT(inc, {B(01000), REG, ImpW(1)})
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INST(aaa, {B(00110111)})
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INST(daa, {B(00100111)})
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INST(sub, {B(001010), D, W, MOD, REG, RM})
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INSTALT(sub, {B(100000), S, W, MOD, B(101), RM, DATA, DATA_IF_W})
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INSTALT(sub, {B(0010110), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(sbb, {B(000110), D, W, MOD, REG, RM})
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INSTALT(sbb, {B(100000), S, W, MOD, B(011), RM, DATA, DATA_IF_W})
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INSTALT(sbb, {B(0001110), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(dec, {B(1111111), W, MOD, B(001), RM})
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INSTALT(dec, {B(01001), REG, ImpW(1)})
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INST(neg, {B(1111011), W, MOD, B(011), RM})
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INST(cmp, {B(001110), D, W, MOD, REG, RM})
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INSTALT(cmp, {B(100000), S, W, MOD, B(111), RM, DATA, DATA_IF_W})
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INSTALT(cmp, {B(0011110), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)}) // NOTE(casey): The manual table suggests this data is only 8-bit, but wouldn't it be 16 as well?
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INST(aas, {B(00111111)})
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INST(das, {B(00101111)})
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INST(mul, {B(1111011), W, MOD, B(100), RM, ImpS(0)})
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INST(imul, {B(1111011), W, MOD, B(101), RM, ImpS(1)})
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INST(aam, {B(11010100), B(00001010)}) // NOTE(casey): The manual says this has a DISP... but how could it? What for??
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INST(div, {B(1111011), W, MOD, B(110), RM, ImpS(0)})
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INST(idiv, {B(1111011), W, MOD, B(111), RM, ImpS(1)})
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INST(aad, {B(11010101), B(00001010)})
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INST(cbw, {B(10011000)})
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INST(cwd, {B(10011001)})
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INST(not, {B(1111011), W, MOD, B(010), RM})
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INST(shl, {B(110100), V, W, MOD, B(100), RM})
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INST(shr, {B(110100), V, W, MOD, B(101), RM})
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INST(sar, {B(110100), V, W, MOD, B(111), RM})
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INST(rol, {B(110100), V, W, MOD, B(000), RM})
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INST(ror, {B(110100), V, W, MOD, B(001), RM})
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INST(rcl, {B(110100), V, W, MOD, B(010), RM})
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INST(rcr, {B(110100), V, W, MOD, B(011), RM})
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INST(and, {B(001000), D, W, MOD, REG, RM})
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INSTALT(and, {B(1000000), W, MOD, B(100), RM, DATA, DATA_IF_W})
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INSTALT(and, {B(0010010), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(test, {B(1000010), W, MOD, REG, RM}) // NOTE(casey): The manual suggests there is a D flag here, but it doesn't appear to be true (it would conflict with xchg if it did)
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INSTALT(test, {B(1111011), W, MOD, B(000), RM, DATA, DATA_IF_W})
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INSTALT(test, {B(1010100), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)}) // NOTE(casey): The manual table suggests this data is only 8-bit, but it seems like it could be 16 too?
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INST(or, {B(000010), D, W, MOD, REG, RM})
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INSTALT(or, {B(1000000), W, MOD, B(001), RM, DATA, DATA_IF_W})
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INSTALT(or, {B(0000110), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(xor, {B(001100), D, W, MOD, REG, RM})
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INSTALT(xor, {B(1000000), W, MOD, B(110), RM, DATA, DATA_IF_W}) // NOTE(casey): The manual has conflicting information about this encoding, but I believe this is the correct binary pattern.
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INSTALT(xor, {B(0011010), W, DATA, DATA_IF_W, ImpREG(0), ImpD(1)})
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INST(rep, {B(1111001), Z})
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INST(movs, {B(1010010), W})
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INST(cmps, {B(1010011), W})
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INST(scas, {B(1010111), W})
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INST(lods, {B(1010110), W})
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INST(stos, {B(1010101), W})
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INST(call, {B(11101000), ADDR, Flags(Bits_RelJMPDisp)})
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INSTALT(call, {B(11111111), MOD, B(010), RM, ImpW(1)})
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INSTALT(call, {B(10011010), ADDR, DATA, DATA_IF_W, ImpW(1)})
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INSTALT(call, {B(11111111), MOD, B(011), RM, ImpW(1), Flags(Bits_Far)})
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INST(jmp, {B(11101001), ADDR, Flags(Bits_RelJMPDisp)})
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INSTALT(jmp, {B(11101011), DISP, Flags(Bits_RelJMPDisp)})
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INSTALT(jmp, {B(11111111), MOD, B(100), RM, ImpW(1)})
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INSTALT(jmp, {B(11101010), ADDR, DATA, DATA_IF_W, ImpW(1)})
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INSTALT(jmp, {B(11111111), MOD, B(101), RM, ImpW(1), Flags(Bits_Far)})
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// NOTE(casey): The actual Intel manual does not distinguish mnemonics RET and RETF,
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// but NASM needs this to reassemble properly, so we do.
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INST(ret, {B(11000011)})
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INSTALT(ret, {B(11000010), DATA, DATA_IF_W, ImpW(1)})
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INST(retf, {B(11001011)})
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INSTALT(retf, {B(11001010), DATA, DATA_IF_W, ImpW(1)})
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INST(je, {B(01110100), DISP, Flags(Bits_RelJMPDisp)})
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INST(jl, {B(01111100), DISP, Flags(Bits_RelJMPDisp)})
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INST(jle, {B(01111110), DISP, Flags(Bits_RelJMPDisp)})
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INST(jb, {B(01110010), DISP, Flags(Bits_RelJMPDisp)})
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INST(jbe, {B(01110110), DISP, Flags(Bits_RelJMPDisp)})
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INST(jp, {B(01111010), DISP, Flags(Bits_RelJMPDisp)})
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INST(jo, {B(01110000), DISP, Flags(Bits_RelJMPDisp)})
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INST(js, {B(01111000), DISP, Flags(Bits_RelJMPDisp)})
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INST(jne, {B(01110101), DISP, Flags(Bits_RelJMPDisp)})
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INST(jnl, {B(01111101), DISP, Flags(Bits_RelJMPDisp)})
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INST(jg, {B(01111111), DISP, Flags(Bits_RelJMPDisp)})
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INST(jnb, {B(01110011), DISP, Flags(Bits_RelJMPDisp)})
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INST(ja, {B(01110111), DISP, Flags(Bits_RelJMPDisp)})
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INST(jnp, {B(01111011), DISP, Flags(Bits_RelJMPDisp)})
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INST(jno, {B(01110001), DISP, Flags(Bits_RelJMPDisp)})
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INST(jns, {B(01111001), DISP, Flags(Bits_RelJMPDisp)})
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INST(loop, {B(11100010), DISP, Flags(Bits_RelJMPDisp)})
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INST(loopz, {B(11100001), DISP, Flags(Bits_RelJMPDisp)})
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INST(loopnz, {B(11100000), DISP, Flags(Bits_RelJMPDisp)})
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INST(jcxz, {B(11100011), DISP, Flags(Bits_RelJMPDisp)})
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INST(int, {B(11001101), DATA})
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INST(int3, {B(11001100)}) // TODO(casey): The manual does not suggest that this intrinsic has an "int3" mnemonic, but NASM thinks so
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INST(into, {B(11001110)})
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INST(iret, {B(11001111)})
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INST(clc, {B(11111000)})
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INST(cmc, {B(11110101)})
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INST(stc, {B(11111001)})
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INST(cld, {B(11111100)})
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INST(std, {B(11111101)})
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INST(cli, {B(11111010)})
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INST(sti, {B(11111011)})
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INST(hlt, {B(11110100)})
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INST(wait, {B(10011011)})
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INST(esc, {B(11011), XXX, MOD, YYY, RM})
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INST(lock, {B(11110000)})
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INST(segment, {B(001), SR, B(110)})
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#undef INST
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#undef INSTALT
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#undef B
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#undef D
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#undef S
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#undef W
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#undef V
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#undef Z
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#undef XXX
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#undef YYY
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#undef RM
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#undef MOD
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#undef REG
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#undef SR
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#undef ImpW
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#undef ImpREG
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#undef ImpMOD
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#undef ImpRM
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#undef ImpD
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#undef ImpS
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#undef DISP
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#undef ADDR
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#undef DATA
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#undef DATA_IF_W
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#undef Flags
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