106 lines
4.7 KiB
Markdown
106 lines
4.7 KiB
Markdown
# 5.x series change log
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This page summarizes the major functional and performance changes in each
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release of the 5.x series.
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All performance data on this page is measured on an Intel Core i5-9600K
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clocked at 4.2 GHz, running `astcenc` using AVX2 and 6 threads.
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<!-- ---------------------------------------------------------------------- -->
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## 5.3.0
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**Status:** March 2025
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The 5.3.0 release is a minor maintenance release.
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* **General:**
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* **Feature:** Reference C builds (`ASTCENC_ISA_NONE`) now support compiling
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for big-endian CPUs. Compile with `-DASTCENC_BIG_ENDIAN=ON` when compiling
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for a big-endian target; it is not auto-detected.
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* **Improvement:** Builds using GCC now specify `-flto=auto` to allow
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parallel link steps, and remove the log warnings about not setting a CPU
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count parameter value.
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* **Bug fix:** Builds using MSVC `cl.exe` that do not specify an explicit
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ISA using the preprocessor configuration defines will now correctly
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default to the SSE2 backend on x86-64 and the NEON backend on Arm64. Previously they would have defaulted to the reference C implementation,
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which is around 3.25 times slower.
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<!-- ---------------------------------------------------------------------- -->
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## 5.2.0
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**Status:** February 2025
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The 5.2.0 release is a minor maintenance release.
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This release includes changes to the public interface in the `astcenc.h`
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header. We always recommend rebuilding your client-side code using the
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header from the same release to avoid compatibility issues.
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* **General:**
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* **Change:** Changed sRGB alpha channel endpoint expansion to match the
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revised Khronos Data Format Specification (v1.4.0), which reverts an
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unintended specification change. Compared to previous releases, this change
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can cause LSB bit differences in the alpha channel of compressed images.
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* **Feature:** Arm64 builds for Linux added to the GitHub Actions builds, and
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Arm64 binaries for NEON, 128-bit SVE 128 and 256-bit SVE added to release
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builds.
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* **Feature:** Added a new codec API, `astcenc_compress_cancel()`, which can
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be used to cancel an in-flight compression. This is designed to help make
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it easier to integrate the codec into an interactive user interface that
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can respond to user events with low latency.
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* **Bug fix:** Removed incorrect `static` variable qualifier, which could
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result in an incorrect `tune_mse_overshoot` heuristic threshold being used
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if a user ran multiple concurrent compressions with different settings.
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<!-- ---------------------------------------------------------------------- -->
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## 5.1.0
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**Status:** November 2024
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The 5.1.0 release is an optimization release, giving moderate performance
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improvements on all platforms. There are no image quality differences.
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* **General:**
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* **Feature:** Added a new CMake build option to control use of native
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gathers, as they can be slower than scalar loads on some common x86
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microarchitectures. Build with `-DASTCENC_X86_GATHERS=OFF` to disable use
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of native gathers in AVX2 builds.
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* **Optimization:** Added new `gather()` abstraction for gathers using byte
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indices, allowing implementations without gather hardware to skip the
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byte-to-int index conversion.
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* **Optimization:** Optimized `compute_lowest_and_highest_weight()` to
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pre-compute min/max outside of the main loop.
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* **Optimization:** Added improved intrinsics sequence for SSE and AVX2
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integer `hmin()` and `hmax()`.
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* **Optimization:** Added improved intrinsics sequence for `vint4(uint8_t*)`
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on systems implementing Arm SVE.
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<!-- ---------------------------------------------------------------------- -->
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## 5.0.0
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**Status:** November 2024
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The 5.0.0 release is the first stable release in the 5.x series. The main new
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feature is support for the Arm Scalable Vector Extensions (SVE) SIMD instruction
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set.
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* **General:**
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* **Bug fix:** Fixed incorrect return type in "None" vector library
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reference implementation.
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* **Bug fix:** Fixed sincos table index under/overflow.
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* **Feature:** Changed `ASTCENC_ISA_NATIVE` builds to use `-march=native` and
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`-mcpu=native`.
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* **Feature:** Added backend for Arm SVE fixed-width 256-bit builds. These
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can only run on hardware implementing 256-bit SVE.
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* **Feature:** Added backend for Arm SVE 128-bit builds. These are portable
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builds and can run on hardware implementing any SVE vector length, but the
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explicit SVE use is augmented NEON and will only use the bottom 128-bits of
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each SVE vector.
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* **Feature:** Optimized NEON mask `any()` and `all()` functions.
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* **Feature:** Migrated build and test to GitHub Actions pipelines.
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- - -
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_Copyright © 2022-2025, Arm Limited and contributors. All rights reserved._
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